The present invention relates to a manufacturing technology of a semiconductor integrated circuit device, particularly to a technology effective when applied to electrical testing of a semiconductor integrated circuit that is carried out by pressing a probe of a probe card against an electrode pad of the semiconductor integrated circuit device.
Japanese Patent Application Laid-open No. 2006-118945 has disclosed a technology, in a prober equipped with a probe (contact terminal), an insulating film and an extraction interconnect and manufactured utilizing the manufacturing technology of a semiconductor integrated circuit device, of inserting a dummy metal film between the extraction interconnect and the probe (contact terminal) to form a space region, thereby adjusting the height of the probe (contact terminal).